Reverse-bias stability and reliability of hole-barrier-free E-mode LPCVD-SiNx /GaN MIS-FETs
2017 IEEE International Electron Devices Meeting (IEDM)(2017)
Abstract
With substantially limited holes generation, the E-mode n-channel LPCVD-SiNx/GaN MIS-FET delivers small NBTI (with V
ds
= 0 V and a negative V
gs
= -30 V) even without a hole-barrier. In high reverse-bias (i.e. high drain bias off-state with V
gs
<; V
th
and large V
ds
) stress, larger negative gate-bias is found to accelerate positive shift in V
th
, suggesting a hole-induced gate dielectric degradation mechanism. It is also revealed that the hole-induced dielectric breakdown can be greatly contained when V
gs
is limited to a few volts below V
th
.
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Key words
gate dielectric degradation mechanism,hole-induced dielectric breakdown,NBTI,reverse-bias stability,n-channel LPCVD MIS-FET,E-mode LPCVD MIS-FET,hole-barrier-free MISFET,negative gate-bias,holes generation,voltage -30.0 V,SiNx-GaN
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