Packaging of 20 kV Double-Side Cooled Silicon Carbide Diode Module With Electrical Insulation Enhanced by a Polymer-Nanoparticle Coating

To address the insulation challenges in packaging medium-voltage silicon carbide power devices, a package design for a 20-kV silicon carbide diode was developed. This design uses a nonlinear resistive polymer-nanoparticle composite to enhance insulation without sacrificing thermal performance. The "sandwich" structure, involving diodes connected between direct-bonded copper substrates, reduces parasitic inductance (<4.5 nH) in a wirebond-less design. This configuration results in a 41% decrease in junction-to-case thermal resistance, according to thermal simulations. Coating electrode triple points with the resistive composite reduces electric field stress. Experimental tests revealed a 96% increase in the partial discharge inception voltage of substrates from 15.6 kV to 30.6 kV. Scaled-down packages with 15 kV silicon carbide diodes was fabricated and tested for validation.