Die-Level Nano-topography Metrology to characterize the stress-induced In-Plane Distortion contribution to overlay

In the field of semiconductor manufacturing, the precise alignment of patterns on a wafer die is critical for the proper functioning of the resulting integrated circuit. However, various factors can cause deformation of the die, which can result in overlay errors and negatively impact device performance. In this work, we focused on the development of die nano-topography metrology, which is used to investigate the topography evolution of five selected dies over several process steps. The impact of manufacturing steps as film deposition, annealing and CMP on die shape deformation and its relation to different pattern densities is measured using optical interferometry. We show that full-die nano-topography measurements are able to detect stress-induced in-plane die distortions as an effect of different annealing processes on SOI or silicon-bulk substrates.