Barrierless ALD Molybdenum for Buried Power Rail and Via-to-Buried Power Rail metallization

2022 IEEE International Interconnect Technology Conference (IITC)(2022)

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摘要
This work reports for the first time, a middle-of-line (MOL) compatible, barrier/liner-less ALD molybdenum (Mo) process on SiO 2 used for Via-to-buried-power-rail (VBPR) and contact-to-active (M0A) dual-damascene metallization. We also compare the MOL-compatible ALD process with the front-end-of-line (FEOL)-compatible ALD process used for BPR fill as reported in [1]. In addition, we report that Mo-BPR can withstand 800 °C anneal, demonstrating its compatibility with high thermal budgets of FEOL. Furthermore, we demonstrate for the first time, integrated (i.e. w/o air-break) precleans prior to Mo-VBPR deposition for contact formation with Mo-BPR. The precleans remove MoO x from Mo-BPR surface proven by SIMS characterization at blanket film level. The effectiveness of precleans is further proven at via level with a good agreement between measured and predicted Mo-VBPR resistance (R) landing on Mo-BPR. Finally, the first downstream electromigration tests on Mo-BPR annealed at 800 °C, show no failures for >150 h at 5 MA/cm 2 & 330 °C proving its robust behavior.
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关键词
CMOS area scaling,ALD Mo,MOL,molybdenum,buried power rail,BPR,scaling booster,A14,A10
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