24.8 A 14nm fractional-N digital PLL with 0.14ps<inf>rms</inf> jitter and −78dBc fractional spur for cellular RFICs

To meet ever-growing demands for higher mobile data-rates, LTE standards continue to evolve. While carrier aggregation (CA) improves data-rates, it requires wider aggregated signal bandwidth that limits the number of users that can be serviced. Techniques like 256QAM and 4×4 MIMO are attractive because improvements do not need wider signal bandwidth. To support 256QAM and 4×4 MIMO for the 5GHz band, we need IPN better than −48dBc or 155fsec rms. A digital fractional-N PLL that achieves 137fsec rms jitter integrating from 10kHz to 10MHz (or 142fsec 1kHz to 10 MHz) with a −78.6dBc near integer-N fractional spur is presented. We have introduced a TDC chopping technique, fine-conversion through SARADCs and TDC nonlinearity calibration to improve IPN and fractional spurs.