An 8x-Osr 25mhz-Bw 79.4db/74db Dr/Sndr Ct Delta Sigma Modulator Using 7b Linearized Segmented Dacs With Digital Noise-Coupling-Compensation Filter In 7nm Finfet Cmos

A low-power and high-dynamic-range downlink ADC is the most critical building block in a cellular receiver design. A continuous-time delta-sigma modulator (CTDSM), which gets the benefit of inherent anti-alias filtering, is a common architecture choice for the ADC. However, low power dissipation dictates a low over-sampling ratio (OSR) since the bandwidth of the loop filter, DAC switching rate, and the clock frequency of the subsequent digital front-end are all proportional to the sampling frequency. Due to the desire for low OSR, a higher quantization level is required to maintain dynamic range, and the successive approximation register (SAR) quantizer, which gets the benefits of power and area efficiency compared to a flash quantizer, becomes more attractive in nanometer processes. However, the issue with a SAR quantizer in a high-speed CTDSM is the limited signal processing time available to achieve lower quantization noise and feedback DAC linearization. In this work, a 12 cycle, 400MHz passive noise-shaping SAR (NS-SAR) is embedded in a low-OSR CTDSM to fulfill the link budget requirement. Two techniques to satisfy the requirement of shorter signal processing time to DAC feedback path are introduced: segmented mismatch error shaping (S-MES) to achieve linear segmented DACs and digital noise coupling compensation filtering (DNCCF) to achieve low quantization noise.