Benchmarking Study on the Thermal Management Landscape for Three-Dimensional Integrated Circuits: From Back-Side to Volumetric Heat Removal

An overview of the thermal management landscape with focus on heat dissipation from three-dimensional (3D) chip stacks is provided in this study. Evolutionary and revolutionary topologies, such as single-side, dual-side, and finally, volumetric heat removal, are benchmarked with respect to a high-performance three-tier chip stack with an aggregate power dissipation of 672 W. The thermal budget of 50 K can be maintained by three topologies, namely: (1) dual-side cooling, implemented by a thermally active interposer, (2) interlayer cooling with four-port fluid delivery and drainage at 100 kPa pressure drop, and (3) a hybrid approach combining interlayer with embedded back-side cooling. Of all the heat-removal concepts, interlayer cooling is the only approach that scales with the number of dies in the chip stack and hence enables extreme 3D integration. However, the required size of the microchannels competes with the requirement of low through-silicon-via (TSV) heights and pitches. A scaling study was performed to derive the TSV pitch that is compatible with cooling channels to dissipate 150 W/cm(2) per tier. An active integrated circuit (IC) area of 4 cm(2) was considered, which had to be implemented on the varying tier count in the stack. A cuboid form factor of 2mm x 4mm x 2.55mm results from a die count of 50. The resulting microchannels of 2mm length allow small hydraulic diameters and thus a very high TSV density of 1837 1/mm(2). The accumulated heat flux and the volumetric power dissipation are as high as 7.5 kW/cm(2) and 29 kW/cm(3), respectively.