RMG nMOS 1^st process enabling 10x lower gate resistivity in N7 bulk FinFETs

A novel RMG process in which the n-type work function metal (nWFM) is deposited first and then selectively removed from the pMOS devices is presented for the first time. The key benefit of this nMOS 1 ^st process lies in increased gate-fill space which results in about 10× improvement in the pMOS effective gate resistivity at gate lengths (L _G ) around 22 nm, an improvement which is predicted by modeling to extend down to L _G <;14 nm. The complete removal of the nWFM in the pMOS devices is evidenced by restored p-type effective work function (eWF) values in large area capacitors and matched pMOS threshold voltage (V _T ) values in bulk FinFET devices with L _G down to 22 nm. Furthermore, selective removal of the nWFM is confirmed physically down to L _G ~16 nm providing further evidence that the process is scalable towards N7 dimensions.