Packaging Of Large-Area, Individually Addressable, Micromirror Arrays For The Next Generation Space Telescope

One of NASA's challenging projects for advancing the exploration of space is the development and deployment of the Next Generation Space Telescope (NGST) for superseding the existing Hubble Space Telescope. The NGST will be equipped with several camera/spectrometer systems including a 0.6 to 5 micron Multi-Object-Spectrometer. To selectively direct light rays from different regions of space into the spectrometer, an option is to use individually addressable micro-electro-mechanical-mirror arrays serving as the slit mask for the spectrometer. The NASA team at Goddard Space Flight Center has designed an integrated micro-mirror array/CMOS driver chip that can meet the system requirements. The fabrication and testing of prototype chips have yielded promising results. To build the entire MEMS-based slit mask, a design requires accurate placement and alignment of four large (at least 9 cm x 9 cm) pieces of the integrated chips in a 2x2 mosaic pattern. In addition, the mask will have to function at temperatures below 40 K. These requirements pose a serious challenge to the packaging of these integrated MEMS chips. In this paper, we discuss a concept for attaching and aligning the large-area MEMS chips into the 2x2 mask and interconnecting it to the rest of the system. The concept makes use of the flip-chip technology to bump-bond the large chips onto a silicon substrate such that the concern for global thermo-mechanical stresses due to mismatched coefficients of thermal expansion between chip and substrate is eliminated. It also makes use of the restoring force of the solder bumps during reflow to self-align the chips. A critical experiment involving the use of "mechanical" chips with two-dimensional arrays of bonding pads was carried out to evaluate the feasibility of the packaging concept. Preliminary results indicate that the chips can be attached to form a closely packed mosaic pattern with a relative tilt angle between the chips to less than 0.05 degree, which is within the system specifications. Modeling results of the thermo-mechanical stresses gave small distortion as a result of local CTE mismatch between the solder bump and silicon when the package is cooled from the solder reflow temperature down to 40 degree Kelvin.