New process of copper pillar bumps on substrate

With the miniaturization, multifunction, high speed development of the chip and package, the requirements for package substrate and 3D packaging becomes higher. As the IC line size continues to decrease, the signal transmission rate continues to improve and the amount and density of pin is getting more and more, the Pad pitch of package substrate which connects to it must be smaller and smaller. The development of package substrate on narrow pitch and low cost Copper pillar bump is becoming more and more important. Copper pillar bump has so many advantages in designs for the next generation of flip chip while it meets current and future ROHS requirements. This is a fabulous choice for actual application, such as transceivers, embedded processors, application processors, power management, baseband ASICs and SOCs where with connation of fine pitch, besides it meets ROHS/Green compliance, low cost and electromigration performance requirement. This article introduces how to process the high density interconnection and small pitch copper pillar bump organic substrate by modified semi-additive process. We have already designed and finished some test boards which narrates how to make copper pillar bump on organic substrate by modified semi-additive process, also it analysis on different packed structures in order to get proper design model, electrical and thermal test. Though these tests we established reliability database with narrower pitch what's more, we improve the First time yield and resolve the difficulties of processing by optimizing the structure and technology. That includes the size, pitch, height and verticality of copper pillar bump.