29.5 A 3nm 3.6ghz Dual-Port SRAM with Backend-RC Optimization and a Far-End Write-Assist Scheme

Hidehiro Fujiwara,Wei-Chang Zhao,Kinshuk Khare, Yi-Hsin Nien,Chih-Yu Lin, Cheng-Han Lin, Shan-Ru Liao, Kenta Torigoe, Shirleen Xia,Yuichiro Ishii, Yao-Yi Lin,Jhon-Jhy Liaw,Yen-Huei Chen,Hung-Jen Liao,Tsung-Yung Jonathan Chang

IEEE International Solid-State Circuits Conference（2025）

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Key words

Dual-port SRAM,Translational Level,Complex Design,Peak Current,Density Data,Design Considerations,Operating Frequency,Voltage Difference,Circuit Design,Resistance Management,Technology Node,Layout Optimization,Sleep Mode,Test Chip,Near-side

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