Monolithic-CFET with Direct Backside Contact to Source/Drain and Backside Dielectric Isolation

A. Vandooren, K. Stiers, C. Sheng,C. Toledo de Carvalho Cavalcante,M. Hosseini,D. Batuk, A. Peng, X. Zhou,H. Mertens,A. Veloso, A. Mingardi, S. Sarkar Kumar, R. Kumar Saroj,K. D'havé,T. Chiarella,J. Bömmels,R. Loo,E. Rosseel,C. Porret,Y. Shimura, A. Akula,S. Choudhury,V. Brissonneau,E. Dupuy, T. Sarkar,A. Peter,N. Jourdan,J.P. Soulie,K. Vandersmissen,S. Iacovo,D. Montero,E. Vrancken,F. Sebaai,P. Puttarame Gowda, K. Lai,N. Buccheri,P. Matagne,B. T. Chan, A. Sepulveda Marquez,R. Langer, I. Gyo Koo,E. Altamirano Sanchez,K. Devriendt,F. Lazzarino,J. Mitard,J. Geypen,E. Grieten, Y-F. Chen, F. Verbeek, H. Pollenus,J. Heijlen,L.P.B. Lima,F. Holsteyns,S. Subramanian,N. Horiguchi,S. Demuynck,S. Biesemans

2024 IEEE International Electron Devices Meeting (IEDM)（2024）

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Key words

Back Side Contact,Si Substrate,Back Side,Higher-order Corrections,Complex Process,Aspect Ratio,Radial Basis Function,Integration Scheme,Atomic Layer Deposition,Front Side,Gate Dielectric,Silicon-on-insulator,Bottom Contact,Cross-sectional TEM

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