Low-Power CMOS Inverter with Enhancement-Mode Operation and Matched $\mathrm{v}_{\text{th}}$ at $\mathrm{v}_{\text{dd}} =1\ \mathrm{v}$ on Monolayer 2D Material Channel

Ang-Sheng Chou,Ching-Hao Hsu, Yu-Tung Lin, Fa-Rong Hou,Edward Chen,Po-Sen Mao, Ming-Yang Li,Sui-An Chou,Dawei Heh,Hsiang-Chi Hu, Yu-Sung Chang, Wen-Chia Wu, Zih-Syuan Huang, Yu-Wei Hsu,Yuan-Chun Su,Terry Y.T. Hung, Po-Hsun Ho,Tsung-En Lee,Chen-Feng Hsu,Goutham Arutchelvan, Yun-Yan Chung,Chao-Hsin Chien,Georgios Vellianitis,Wei-Yen Woon,Jin Cai,Mark van Dal,Wen-Hao Chang,Chih-I Wu,Chao-Ching Cheng,Iuliana P. Radu

2024 IEEE International Electron Devices Meeting (IEDM)（2024）

Cited 0|Views4

Key words

2D Materials,NOT Gate,Monolayer 2D Materials,Enhancement-mode Operation,Threshold Voltage,Transition Metal Dichalcogenides,Switching Voltage,Channel Material,Static Power Consumption,Atomic Force Microscopy,Power Consumption,Chemical Vapor Deposition,Carrier Mobility,High Gain,Wet Process,Key Metrics,Invertible Operator,Transition Metal Dichalcogenides Materials

AI Read Science

Must-Reading Tree

Example

Generate MRT to find the research sequence of this paper

Chat Paper

Summary is being generated by the instructions you defined