A 0.41-Ns CLK-OUT Delay, 0.22-Μvrms Input-Referred Noise CMOS Integration Dynamic Comparator with Flipping Capacitor for Charge Reuse

Kwok Cheong Li,Xinhang Xu,Jihang Gao,Siyuan Ye,Jiajia Cui,Yacong Zhang,Ru Huang,Linxiao Shen

IEEE SOLID-STATE CIRCUITS LETTERS（2025）

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Key words

Noise,Delays,Latches,Capacitors,MOS devices,Solid state circuits,Preamplifiers,Power demand,Logic,Inverters,Charge reuse,CMOS integration,dynamic comparator,flipping capacitor,high speed

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