A 2 Hz, 1.2-2 V, 0.22-9 Nw, 0.007 Mm2 65 Nm CMOS Multiple- Output Down-Converter-Less Clock Generator Using Stacked an Oscillator and Frequency Dividers for Scaling-Friendly IoTs

You Wu, Kei Awano, Kento Okamura, Teruaki Ono, Kohei Sakamoto, Hiroaki Kitaike, Hironori Tagawa,Jin Nakamura,Masaya Kaneko, Yuta Kimura, Hiroaki Nakamura,Shufan Xu,Ruilin Zhang,Kunyang Liu,Hirofumi Shinohara,Kiichi Niitsu

IEEE Nordic Circuits and Systems Conference（2024）

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Key words

Clock generation,Timer,IoT,Charge Recycling,CMOS,65 nm CMOS

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