Patterning Process and Electrical Yield Optimization at the Limits of Single Exposure EUV 0.33 NA: a Pitch 26nm Damascene Process

V.M. Blanco Carballo, K. Vandersmissen. B. De Wachter,K. Nafus,Y. Feurprier, A. Thiam, A. Hsu,C. Tabery, J. Doise,P. De Schepper

2024 IEEE International Interconnect Technology Conference (IITC)（2024）

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Key words

Optimization Process,Single Exposure,Processing Steps,Oxide Layer,Electrical Measurements,Polishing Step,Baking Process,Field Width

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