A Type-II Reference-Sampling PLL with Non-Uniform Octuple-Sampling Phase Detector Achieving 55-Fs JitterRMS, –91.9-Dbc Reference Spur and –259-Db Jitter-Power FOM

Hongyu Ren,Yunbo Huang,Zunsong Yang, Tianle Chen, Xianghe Meng,Weiwei Yan, Weidong Zhang, Zhongmao Liu,Tetsuya Iizuka,Pui-In Mak,Yong Chen, Bo Liu

2024 50TH IEEE EUROPEAN SOLID-STATE ELECTRONICS RESEARCH CONFERENCE, ESSERC 2024（2024）

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Key words

Phase-Locked Loop (PLL),Clock Generator,Frequency Synthesizer,Reference Sampling,Type-II,Low Jitter,Low Power,Low Spur

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