A 6.5-to-6.9-ghz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-Fs RMS Jitter, -260.7-db FOMJitter, and -76.5-dbc Reference Spur

Tianle Chen, Hongyu Ren,Zunsong Yang,Yunbo Huang, Xianghe Meng,Weiwei Yan, Weidong Zhang,Xuqiang Zheng,Xuan Guo,Tetsuya Iizuka,Pui-In Mak, Yong Chen,Bo Li

Symposium on VLSI Technology（2024）

Cited 0|Views8

Key words

Rms Jitter,Reference Spur,Subsampling Phase-locked Loop,Sub-sampling Phase Detector,Phase Noise,Phase-locked Loop,Even And Odd,Reference Input,Total Power Consumption,65-nm CMOS,Reference Buffer,Odd Mode

AI Read Science

Must-Reading Tree

Example

Generate MRT to find the research sequence of this paper

Chat Paper

Summary is being generated by the instructions you defined