Ultra Low Power High Speed DFT Implementation For ASIC SoC

An ultra-low power DFT architecture suitable for MIMO-OFDM applications & it was introduced in this study. Several radix such as 8/16/32 dependent optimization methods are performed to create variable lengths of 4k/8k points, a necessity in today's 4G and 5G communication technologies, which are plagued by a number of power and performance concerns with DFT processors. These technologies are widely used but have a higher energy footprint than others. Consequently, this work uses a novel approach called "SBOX" and the concept of parallelism to boost performance and reduce power consumption, all of which are essential for an advanced DFT architecture. Parallelism and the proposed SBOX model allow for fewer multiplications and faster processing times. Cadence-allegro-17.2 is used for the design and verification of the full implementation; this software is also used for simulation, synthesis, layout, and power analysis. The area required for 8-point s-box DFT is 105.15 um2, it requires 7mW of power, and it can achieve a throughput of 59.33GBPS. In addition, the throughput of 57.33GBPS may be achieved by 16-point s-box DFT with a footprint of 123.35um2, using 9mW of power. Also, the throughput of 32-point s-box DFT is 56.45GBPS on a chip that uses 10.24 mW and occupies 132.35um2. With MIMO in 5G technology, this layout becomes more practical for usage in telecommunications. The performance is enhanced over existing architectures thanks to the optimized radix 8 s-box DFT.