Testing for Electromigration in Sub-5nm FinFET Memories

Higher integration density and reduced pitch size in advanced technology nodes result in higher current densities in interconnects, leading to aggravated interconnect aging known as electromigration (EM). Since the correct functionality of Static RAM (SRAM) in advanced nanoscale interconnect-dominant technologies is significantly more sensitive to interconnect parameters, small resistance increase due to EM can lead to infield failures. Early EM detection is crucial for preventative maintenance in safety-critical applications such as automotive systems. This paper proposes an effective EM test method for real-world SRAM macros in 5 nm FinFET technology.