PolyLUT-Add: FPGA-based LUT Inference with Wide Inputs
CoRR(2024)
Abstract
FPGAs have distinct advantages as a technology for deploying deep neural
networks (DNNs) at the edge. Lookup Table (LUT) based networks, where neurons
are directly modelled using LUTs, help maximize this promise of offering
ultra-low latency and high area efficiency on FPGAs. Unfortunately, LUT
resource usage scales exponentially with the number of inputs to the LUT,
restricting PolyLUT to small LUT sizes. This work introduces PolyLUT-Add, a
technique that enhances neuron connectivity by combining A PolyLUT
sub-neurons via addition to improve accuracy. Moreover, we describe a novel
architecture to improve its scalability. We evaluated our implementation over
the MNIST, Jet Substructure classification and Network Intrusion Detection
benchmark and found that for similar accuracy, PolyLUT-Add achieves a LUT
reduction of 1.3-7.7× with a 1.2-2.2× decrease in latency.
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