FASQuiC: Flexible Architecture for Scalable spin Qubit Control

As scaling becomes a key issue for Large Scale Quantum (LSQ) computing, hardware control systems will become increasingly costly in resources. This paper presents a compact Direct Digital Synthesis (DDS) architecture for signal generation adapted for spin qubits, which is scalable in terms of waveform accuracy and the number of synchronized channels. The architecture can produce programmable combinations of ramps, frequency combs and Arbitrary Waveform Generation (AWG) at 5 GS/s, with a worst-case digital feedback latency of 76.8 ns. The FPGA-based system is highly configurable and takes advantage of bitstream switching to achieve the high flexibility required for scalable calibration. The architecture also provides GHz rate multiplexed I/Q single-side band (SSB) modulation for scalable reflectometry. This architecture has been validated in hardware on a Xilinx ZCU111 FPGA demonstrating the mixing of complex signals and the quality of the frequency comb generation for multiplexed control and measurement. The key benefits of this design are the increase of controllability of ramps at the Digital to Analog Converter (DAC) frequency and the reduction in memory requirements by several orders of magnitude compared to existing AWG-based architectures. The hardware for a single channel is very compact, 2% of ZCU111 logic resources for one DAC lane in the default configuration, leaving significant circuit resources for integrated feedback, calibration and Quantum Error Correction (QEC).