Massive MIMO-ISAC System With 1-Bit ADCs/DACs
arxiv(2024)
Abstract
This paper investigates a hardware-efficient massive multiple-input
multiple-output integrated sensing and communication (MIMO-ISAC) system with
1-bit analog-to-digital converters (ADCs)/digital-to-analog converters (DACs).
The proposed system, referred to as 1BitISAC, employs 1-bit DACs at the ISAC
transmitter and 1-bit ADCs at the sensing receiver, achieving significant
reductions in power consumption and hardware costs. For such kind of systems,
two 1BitISAC joint transceiver designs, i.e., i) quality of service constrained
1BitISAC design and ii) quality of detection constrained design, are considered
and the corresponding problems are formulated. In order to address these
problems, we thoroughly analyze the radar detection performance after 1-bit
ADCs quantization and the communication bit error rate. This analysis yields
new design insights and leads to unique radar and communication metrics, which
enables us to simplify the original problems and employ
majorization-minimization and integer linear programming methods to solve the
problems. Numerical results are provided to validate the performance analysis
of the proposed 1BitISAC and to compare with other ISAC configurations. The
superiority of the proposed 1BitISAC system in terms of balancing ISAC
performance and energy efficiency is also demonstrated.
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