Inflection Points in Cfet Scaling: Impact of Dtco Boosters
2024 Conference of Science and Technology for Integrated Circuits (CSTIC)(2024)
摘要
Complimentary FETs (CFETs) enable aggressive standard cell height (CH) reduction, facilitating on-target area scaling without shrinking contacted gate pitch (CGP). We extensively benchmark nanosheet (NS) based CFETs against gate-all-around (GAA) NSFETs using power, performance, area (PPA) as well as scalability metrics. The impact of BEoL RC, new materials, DTCO boosters is further explored. 4T CFET designed with 20 nm metal pitch (MP) offers 62% smaller area and 28% extra speed at iso-power over reference NS devices.
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关键词
Inflection Point,Standard Height,Parasite,Gating Process
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