A Study of the Via Pattern Lithography Process Window Under the 7 NM Logic Design Rules With 193 NM Immersion Lithography

The rapid advancement of integrated circuit technology has imposed increasingly stringent process constraints within photolithography, driven by the escalating requirements for higher integration levels in chip manufacturing. Due to the two-dimensional nature of vias, their minimum pitch exceeds that of metals, resulting in complex mask decomposition. Therefore, understanding the size constraints of typical via patterns in a single exposure becomes crucial, for simplifying the exposure process of the via layer and reducing manufacturing costs. In this paper, we discuss several patterns under 7 nm logic design rules with a Minimum Metal Pitch (MMP) of 40 nm. The simulation results suggest that when the pitch is 113 nm, the process window nears the recommended value necessary for actual photolithography processes. Additionally, for larger pitch via patterns, manufacturing requirements can still be met.