A novel test structure with two active areas for eNVM reliability studies
2024 IEEE 36th International Conference on Microelectronic Test Structures (ICMTS)(2024)
摘要
This paper presents a test structure with a poly floating gate shared on two actives areas. Programming and erase can be split toward these two regions with a specific arsenic implantation. The aim is to study the tunnel oxide degradation and the injection efficiency of embedded charge storage memory cells.
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