Modeling methodology for multi-die chip design based on gem5/SystemC co-simulation

The paper introduces a modeling methodology aimed at thoroughly exploring the design space of multi-die chip architecture tailored for High-Performance Computing (HPC). For accurate simulations, we leverage the capabilities of gem5's Ruby for its robust CPU models and cache coherence protocols, providing a comprehensive representation of die architecture. Die-to-die interfaces are modeled using SystemC TLM, offering flexibility to integrate with other simulators. This enables co-simulation with varying abstraction levels, making it well-suited for the design analysis of multi-die chip architecture. We present, to the best of our knowledge, the first attempt to integrate gem5's Ruby memory system with SystemC TLM for the modeling of multi-die chip architecture. The benefits of this model are demonstrated through the instantiation of a multi-die design using modern Arm architectures with four compute dies and twoexecuting STREAM Triad with Linux, followed by a comparative performance analysis against a monolithic design.