CMOS-RRAM based In-Memory Hamming Distance Calculation Technique

We designed a CMOS-RRAM based in-memory Hamming Distance (HD) calculation technique providing additional degree of mismatch as compared to Content Addressable Memories (CAMs). One 2T2R (2-Transistor, 2-RRAM) cell is considered to store a single encoded bit of ternary information, while both the RRAM cells are programmed to complementary resistance states. The net current flowing through the 2T2R unit cell results in the HD. Moreover, the HD for various possible combinations of 16-bit input and stored data was shown through array level circuit simulations with integrated Transimpedence Amplifiers (TIAs) to convert row-wise accumulated current into output voltage. The 2T2R-based technique exhibits minimum $3\times$ area and $\geq 3.6\times$ power saving as compared to existing CMOSNVM (Non-Volatile Memory) counterparts.