Soft and Hard Error Correction Techniques in STT-MRAM

IEEE Design & Test(2024)

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摘要
Spin-transfer torque magnetic random access memory (STT-MRAM) has emerged as a promising alternative to conventional CMOS memory technologies. It offers non-volatility, low power consumption, and scalability and has gained significant industrial maturity, with several foundries now offering this technology. However, the reliability challenges associated with STT-MRAM can overshadow its benefits. Soft errors, including resistance drift and read and write disturbances, pose significant challenges to data integrity and system stability in STT-MRAM. Moreover, STT-MRAM is also susceptible to other failure mechanisms, such as manufacturing defects in CMOS and magnetic layers, temperature variations, repetitive writes, and oxide breakdown. These failure mechanisms can lead to hard errors or permanent faults during manufacturing and the lifetime operation of the memory system. Such issues impair the manufacturing yield and hinder the large-scale industrial adoption of STT-MRAM. This paper presents a comprehensive study and survey of techniques to improve the manufacturing yield and in-field reliability of STT-MRAM while addressing both soft and hard errors. By categorizing the research works based on critical parameters such as error types, mitigation strategies, and system-level considerations, a detailed overview of state-of-the-art techniques to enhance STT-MRAM reliability is provided.
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关键词
Spin-transfer torque magnetic random access memory (STT-MRAM),non-volatile memories (NVMs),reliability,error correcting codes (ECCs),single error correction-double error detection (SEC-DED),soft error,hard error
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