Power Efficient Hardware Fingerprint: Exploiting Process-Variations in A Quasi-Planar 14nm FinFET.

This research paper introduces a low-power Physically Unclonable Function (PUF) design utilizing well-calibrated 14 nm FinFET technology. By leveraging the inherent process variations encountered during FinFET fabrication, the design exploits the uniqueness of each device. The implementation involves using a lookup table-based approach in the Cadence Virtuoso environment to create FinFET based inverters. To describe the low power consumption of FinFET technology, first, this research focuses on constructing a 3-stage Ring Oscillator (RO) with a power dissipation of 64.2 $\mu \mathrm{W}$ . Additionally, a significant contribution of this work is the development of a 32-bit PUF circuit, which utilizes 64 of these ROs. This novel design takes advantage of the quasi-planar structure and increased process variability offered by the 14 nm FinFET technology. The integration of these components enables efficient power utilization while maintaining the desired PUF functionality. To assess the uniqueness of the responses generated by 120 different PUFs, Monte Carlo simulations are conducted on 7680 points. The hamming distance between the generated response pairs is employed to quantify the uniqueness, resulting in an observed value of 50.05%. Additionally, an entropy evaluation is performed, yielding a calculated entropy of 0.987. Furthermore, a comparative analysis provides valuable insights by comparing the work presented with prior research contributions.