Importance of Scaling in RF GaN HEMTs for Reduction of Surface Traps-Induced Drain Lag

Drain lag is a well-known phenomenon that leads to radio frequency performance degradation in AlGaN/GaN high-electron-mobility transistors. Herein, it is demonstrated that a reduction of the gate-to-drain distance (Lgd) from 2.0 to 0.5 mu m results in 7% reduction in the current collapse. This improvement is attributed to a decrease in surface trapping, which, in this case, is found to have a greater impact on current collapse than relatively slow traps in the buffer layer. To support this argument, TCAD simulations are conducted. Load-pull analysis confirms that scaling the devices to Lgd = 0.5 mu m provides 15% better output power density at 10 GHz than Lgd = 2.0 mu m. Additionally, a new passivation layer for reduced surface traps exhibits a 20 to 30% higher output power density and at least a 10% improvement in power-added efficiency at 20 GHz on a nominally identical GaN-on-semi-insulating SiC epi-wafer. This study explores theeffects of SiN-based passivation layers and gate-drain distances (Lgd) on the large signal performance of GaN HEMT devices, underscoring thesignificant role of surface traps. It is demonstrated that either improvingpassivation quality or reducing the gate-drain can mitigate trapping effects. Measured and simulated drainlag versus Lgd in reference wafer (W1) and developed technology (W2).image (c) 2024 WILEY-VCH GmbH