Efficient Majority Logic Parallel-Prefix Adder Design

Beyond CMOS nanotechnology has been attracted interest by many researchers. The logical fundamental elements of many nanotechnologies are the majority, minority gates and inverters. The design of efficient adder systems and especially the parallel prefix adders is of very importance. In this paper efficient majority logic implementation of parallel prefix is introduced. The proposed methodology can be generalized to any parallel prefix structure design. Moreover, the proposed majority logic parallel prefix adder designs demonstrate decreased circuit complexity when compared to the literature.