Conceptual Design and Analysis of a Cryogenic Front-End ASIC for TES Readout Using ST-130 nm BiCMOS Technology

In the context of future ground-based or space-borne cryogenic instruments using transition-edge sensors (TES), the location of the front-end electronics (FEEs) is an important aspect of instrument design. The main functions of the FEE are to provide biasing currents for TES and superconducting quantum interference devices (SQUIDs) and to amplify the output signals of the SQUID arrays (the last SQUID stage). Room temperature FEE has several advantages compared to cryogenic FEE: more power available, characterized commercially available devices, easier to develop and test, etc. On the other hand, it usually means having a longer cryo-harness before large signal amplification and more complex cryostat interfaces to preserve small signal integrity. Moreover, it is generally assumed that cooling the readout improves the intrinsic noise in addition to avoid interference in the cryo-harness. In this paper, we present a conceptual design of an application-specific integrated circuit (ASIC) for TES front-end readout operating at cryogenic temperatures (50–70 K) using ST-130 nm technology. We discuss the necessary steps for the development of such ASICs. Indeed, another ASIC integrating elementary components has already been developed with this technology and has been tested at cryogenic temperatures. The measurements as function of temperature are useful to determine the correct operating points for low-temperature optimal performances of an FEE. Finally, the impacts of cryogenic operations on noise are discussed.