A 20-Gb/s Jitter-Tolerance-Enhanced Digital CDR With One-Tap DFE

Wei-Ming Chen,Yun-Sheng Yao,Shen-Iuan Liu

IEEE Transactions on Circuits and Systems II: Express Briefs（2022）

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摘要

A digital clock/data recovery (CDR) circuit with a one-tap speculative decision feedback equalizer (DFE) and a calibration circuit is presented. This CDR circuit is fabricated in 40-nm CMOS technology and its active area is 0.1 mm2. For a channel loss of −10.31dB at 10GHz and a 20Gb/s PRBS of $2^{7}-1$ , the measure...

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关键词

Calibration,Threshold voltage,Clocks,Decision feedback equalizers,Timing,Codes,Generators

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