Understanding HZO Thickness Scaling in Si FeFETs: Low Operating Voltage, Fast Wake-Up, and Suppressed Charge Trapping

IEEE TRANSACTIONS ON ELECTRON DEVICES(2024)

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摘要
Hf-0.5 Zr-0.5 O-2 (HZO)-based ferroelectric field effect transistor (FeFET) has been recognized as a promising nonvolatile memory due to its excellent scalability and CMOS process compatibility. To realize memory operation with low operating voltage, it is essential to gain a systematic understanding of HZO scaling effects, especially under the thickness of HZO < 10 nm conditions. In this work, we study n-FeFET with HZO thickness ranging from 4.1 to 11 nm and analyze the HZO scaling effects in FeFET. Differing from metal-ferroelectric-metal (MFM) with thin HZO, FeFET with thin HZO shows no strong wake-up effect. Besides, the low-voltage operation, low subthreshold swing (SS) value, and higher current memory window (MW) (or Undefined control sequence \biosc / Undefined control sequence \biosc ratio) brought by HZO scaling are revealed. Moreover, the lower charge trapping density is observed in FeFETs with HZO thinner than 10 nm and improved read-after-write delay is observed in 5.2-nm FeFET. This work sets up a systematical direction for understanding the scaling impacts of HZO on the electrical characteristics of Si FeFET.
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关键词
FeFETs,Iron,Films,Low voltage,Voltage,Silicon,Annealing,Charge trapping density,ferroelectric field effect transistor (FeFET),Hf-0.5 Zr-0.5 O-2 (HZO),low-voltage operation,subthreshold swing (SS),thickness scaling
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