SOT-MRAM Based LUT Cell Design for Area and Energy Efficient FPGA

Although SOT-MRAM based non-volatile lookup tables (LUTs) can be efficiently employed to reduce the area of field programmable gate array (FPGA), the selector containing the multiplexer (MUX) tree for accessing the LUT cells still takes a dominant portion of LUT area. In this paper, we present a novel area-efficient SOT-MRAM-based LUT that can efficiently re-move the last stage selector. In the proposed LUT, the role of the last stage selector, which is selecting a cell among the preceding two cells, has been implemented using SOT-MRAM cell with additional vertical metal lines within the LUT cell. The control of the metal lines requires only a small number of switches and controller, incurring minor hardware resources compared to the last stage selector MUX tree. As a result, almost half of the entire MUXs in the selector can be eliminated and significant area reduction can be achieved. In addition, the proposed LUT cell also offers an improvement in read energy and speed by reducing the BL capacitances of the metal lines involved in the read operations. The post-layout simulation results using 28nm CMOS process show that the proposed SOT-MRAM LUT design achieves 34.1% of area and 20.1% read energy reduction with 22.1% read speed improvement when compared to conventional SOT-MRAM based LUT.