Double Self-Aligned Contact Patterning Scheme for 3D Stacked Logic and Memory Devices

This paper presents a new patterning scheme that allows self-alignment of active area contacts at different z-elevations. This patterning approach can be used for various types of 3D logic and memory devices. From an incoming structure using a stack of materials with different etch selectivity, some local metal braces are first introduced at certain targeted elevations and provide a first level of contact to active device materials. The brace formations require diverse etch selectivity for the selected dielectric materials, ultra-conformal metal deposition techniques for use on buried/covered structures, and anisotropic metal etching steps. A second level of contact is then made to access those braces by using via and cavity etches followed by metal fill. This multi-level contact patterning technique is further described in this paper by first using a generic example, and then by looking at two specific applications for logic and memory, with new CFET and staircase contacting schemes, respectively.