(ESCS'23: Poster Paper) Improving Energy Efficiency of RISC-V Processor for Sensor Node

Sensor nodes are developing from low-bandwidth data intermediaries to endpoint data analysis devices that execute complicated algorithms on high-bandwidth data streams coming from smart sensors. These devices must work within strict performance and power constraints. This calls for careful designing of processors which are energy efficient to ensure long lasting performance of sensors. In this paper, we aim at optimizing a RISC-V processor design in order to achieve an energy efficient processor which can be used in sensor nodes. The design is implemented using various RTL power reduction methods. Sleep unit is designed to control the core clock. Simulation is performed to understand the functionality of the design. Power and timing analyses are also presented.