High-throughput and fully-pipelined ciphertext multiplier for homomorphic encryption

Homomorphic Encryption (HE) has become a promising technique to protect the data privacy in cloud computing, while its slow speed highly restricts the application. We propose a high throughput and fully pipelined implementation of ciphertext multiplier on FPGA to accelerate ciphertext multiplication, which is one of the frequently performed operations in HE applications and takes most of the calculation time. The fully pipelined architecture avoids memory access conflict and minimizes the memory usage on chip. Consequently, the logic cells, including LUTs and DSPs, are efficiently utilized for high parallelism degree and high throughput is achieved. The throughput is increased to 4.7 times compared to state -of -art FPGA designs and 1340 times of CPU performance.