Aninterstage gaincalibration technique for pipelined ADCs exploiting Complementary ditheringandcalibration windowsdetector

In thispaper, a complementary ditheringtechnique is proposed which utilizes LMSdigital background calibration methodto correct the interstage gain errors in pipeline analog-to-digital converters (ADCs). Itnot only has a better scattering effect on spectral spurs but also eliminatesthe increment of residual amplitudecaused by ditherinjection, which will greatly alleviate the design requirements of residual amplifier. Simultaneously, the comparator resolving timenature is utilized to construct calibration windows, which averts the use of duplicate comparatorsand its digital logic is simple.Behavioral simulation results of 12-bit, 1.25GS/s pipelined ADC manifestthat the proposedcalibration techniqueenhancesSNDRand SFDR from 44.27dBand 49.43dB to 70.8dBand 115.3dB respectively