A pathway to improve short channel effects of junctionless based FET's after incorporating technology boosters: a review

The Short Channel Effects (SCE) are becoming more prominent in Complementary Metal Oxide Semiconductor (CMOS) circuits with the introduction of nanoscale Metal Oxide Semiconductor Field Effect Transistors (MOSFET). The short channel effects (SCE's) and fabrication challenges have provoked the researchers to think of some other technologies to enhance the market of semiconductor devices. To overcome these SCE's, various methodologies such as multi-gate structures, material engineering, gate engineering, dielectric pockets, strain technology, high K dielectric material, heterostructures, source and drain extensions etc have been implemented. However, at very short channel lengths, the sharp edges of doping are difficult to obtain and thus SCE's have become so difficult to control even after the implementations of different methodologies. Therefore, a new type of technology has been introduced to overcome such pitfalls e.g. transistors without junctions. Junctionless field effect transistor (JLFET) is one of the technologies which has overcome various SCE's. Although the research on various issues has been addressed by different authors, there is still an impediment to the commercialization of the same device. The different technology boosters have been incorporated into junctionless-based devices to escalate the performance. The technology-boosting aspect of junctionless FET has been reviewed in this paper which has not been considered yet. In this paper distinct technology boosters and numerous effects on junctionless devices have been studied and presented. The performance of the junctionless FET devices is studied by incorporating the different semiconductor materials, effect of strain, use of high k dielectric, use of dielectric pockets, effect of gate misalignment, use of heterostructures, silicon on nothing (SON), vertically stacked nanowires, newly proposed rectangular core-shell based junctionless FET's and roles of various physical parameters such as temperature, nanowire widths and effect of scattering mechanism on the performance of JLFET have been addressed.