A 3-nm FinFET 27.6-Mbit/mm²Single-Port 6TSRAM Enabling 0.48-1.2 V Wide OperatingRange With Far-End Pre-Charge andWeak-Bit Tracking

A 3-nm FinFET single-port (SP) 6T SRAM macrois proposed that utilizes a far-end pre-charge (FPC) circuit and weak-bit (WB) tracking circuit. These circuits can decrease write cycle time by decreasing the pre-charge period and engagingread cycle time by enhancing the trackability of sense enabletiming over supply voltage. A prototype of the 434-kbit SP SRAMmacro on 3-nm FinFET technology was designed and fabricated. The bit density is 27.6 Mbit/mm(2)and it achieved an operation of 1.9 GHz at 0.75 V and 85(degrees)C, which is 35% faster than conventional performance. Measured silicon data demonstrate a wide operating voltage range of 0.48-1.2 V. This proposal hasalso achieved the best figure of merit (FoM) compared to other works, as defined by densityxaccess per second (APS)/supply voltage (V-DD).