A 3-nm FinFET 27.6-Mbit/mm2Single-Port 6TSRAM Enabling 0.48-1.2 V Wide OperatingRange With Far-End Pre-Charge andWeak-Bit Tracking
IEEE JOURNAL OF SOLID-STATE CIRCUITS(2024)
Abstract
A 3-nm FinFET single-port (SP) 6T SRAM macrois proposed that utilizes a far-end pre-charge (FPC) circuit and weak-bit (WB) tracking circuit. These circuits can decrease write cycle time by decreasing the pre-charge period and engagingread cycle time by enhancing the trackability of sense enabletiming over supply voltage. A prototype of the 434-kbit SP SRAMmacro on 3-nm FinFET technology was designed and fabricated. The bit density is 27.6 Mbit/mm(2)and it achieved an operation of 1.9 GHz at 0.75 V and 85(degrees)C, which is 35% faster than conventional performance. Measured silicon data demonstrate a wide operating voltage range of 0.48-1.2 V. This proposal hasalso achieved the best figure of merit (FoM) compared to other works, as defined by densityxaccess per second (APS)/supply voltage (V-DD).
MoreTranslated text
Key words
Random access memory,Delays,Voltage,FinFETs,Timing,Resistance,Market research,3 nm,bitcell (BC),cache,far-end pre-charge (FPC),FinFET,high current (HC),multi-bank,single port (SP),SRAM,weak-bit (WB) tracking
AI Read Science
Must-Reading Tree
Example
Generate MRT to find the research sequence of this paper
Chat Paper
Summary is being generated by the instructions you defined