Source Design of Vertical IIICV Nanowire Tunnel Field-Effect Transistors

We systematically fabricate devices and analyze data for vertical InAs/(In)GaAsSb nanowiretunnel field-effect transistors (TFETs), to study the influence of source dopant position and level on theirdevice performance. The results show that delaying the introduction of dopants further in the GaAsSb sourcesegments improved the transistor metrics (subthreshold swing (SS) and the on-current performance), due tothe formation of a nid-InAsSb segment. The devices display a minimum SS of 26 mV/dec and on-current of10.2 mu A/mu m atVDSof 300 mV. The performance of devices were improved further by optimizing the dopinglevels which led to record subthermal current of 1.2 mu A/mu m and transconductance of 205 mu S/mu m atVDSof500 mV.