A 10-bit 13.3 μW single-slope analog-to-digital converter with auto-zero power-down technique

This letter presents a low-power single-slope analog-to-digital converter (ADC) for column-parallel architectures. A simple and effective design technique is proposed to solve the input-dependent power consumption problem of the conventional single-slope ADCs. A decision-feedback loop is implemented in the second stage of the comparator. Based on the negative-feedback path, which is activated after the signal decision of the comparator, the input-dependent dynamic current path in the amplifier is disabled. Furthermore, an additional low-power design technique is proposed to save the power consumption of the ADC by optimizing the offset cancelling auto-zero period. With the combination of the proposed techniques, the power consumption of the single-slope ADC can be effectively saved while suppressing the dynamic current. Based on the negative-feedback path, which is activated after the signal decision of the comparator, the input-dependent dynamic current path in the amplifier is disabled. Furthermore, an additional low-power design technique is proposed to save the power consumption of the analog-to-digital converter (ADC) by optimizing the offset cancelling auto-zero period. With the combination of the proposed techniques, the power consumption of the single-slope ADC can be effectively saved while suppressing the dynamic current. image