Parallel refreshed cryogenic charge-locking array with low power dissipation
arxiv(2024)
摘要
To build a large scale quantum circuit comprising millions of cryogenic
qubits will require an efficient way to supply large numbers of classic control
signals. Given the limited number of direct connections allowed from room
temperature, multiple level of signal multiplexing becomes essential. The
stacking of hardware to accomplish this task is highly dependent on the lowest
level implementation of control electronics, of which an open question is the
feasibility of mK integration. Such integration is preferred for signal
transmission and wire interconnection, provided it is not limited by the large
power dissipation involved. Novel cryogenic electronics that prioritises power
efficiency has to be developed to meet the tight thermal budget. In this paper,
we present a power efficient approach to implement charge-locking array.
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