The Significance of Thermal-Aware Universal Chiplet Interconnect Express (UCIe) Interface Design in 2.5D/3D ICs
2023 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)(2023)
摘要
In this paper, signal integrity analysis of universal chiplet interconnect express-advanced (UCIe-A) interface in terms of crosstalk and thermal effects was carried out. As the demands of chiplet systems increase, the need for strong interconnectivity with each chiplet intensifies. UCIe-A is the chiplet-to-chiplet interconnect on advanced package which supports high datarate of 32 Gb/s within small PHY dimension. Therefore, the crosstalk of UCIe-A channel is the dominant signal integrity design issue. Furthermore, as the power consumption of chiplet increases, thermal management of chiplet system becomes more challenging, leading to an increase in temperature along the interconnect. Thermal issue is particularly severe in 2.5D/3D ICs, where the elevated temperatures can significantly degrade signal integrity. Hence, this research focused on the thermal effects on signal integrity of the UCIe-A interface, in terms of channel characteristics, voltage transfer function, and eye-diagrams. The results show that the thermal effect on UCIe-A interface surpasses the crosstalk effect at 80°C. This research validates the significance of thermal-aware UCIe-A interface design for chiplet systems.
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关键词
Advanced package,Chiplet,Crosstalk,Thermal-aware,Universal chiplet interconnect express (UCIe)
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