2.7 BayesBB: A 9.6Gbps 1.61ms Configurable All-MessagePassing Baseband-Accelerator for B5G/6G Cell-Free Massive-MIMO in 40nm CMOS

The global success of 5G wireless exerts a significant impact on human life [1]. For the forthcoming beyond-5G (B5G) and 6G eras [2], there is demand for wireless networks to evolve from consumer applications towards production-centric demands, to provide comprehensive support to diverse vertical industries. Hence, cell-free massive MIMO [3] has emerged as a crucial catalyst for B5G/6G, delivering magnitudes’ higher spectrum efficiency (SE). B5G/6G expects baseband (BB) chips that can simultaneously offer improved throughput (higher than 8Gbps/user), ultra-low latency (less than 2ms), and flexible multi-application support (with exceptional configurability). Existing literature mainly emphasizes individual BB modules [4] –[6], like MIMO detectors, channel decoders or their combination. Thus, a system-level BB chip that can deliver satisfactory performance in terms of high throughput, low latency, and adaptability to various applications is desirable for B5G/6G [2]. As shown in Fig. 2.7.1, the utilization of such a system-level BB chip poses three challenges: 1) Achieving high throughput is demanding, as it involves designing a high-speed interface that can not only handle the anticipated increase in B5G/6G data traffic, but also adhere to the IEEE 802.3 standard. 2) Ensuring low latency is challenging, because it requires incorporating various algorithms into a single BB chip, while meeting the stringent time requirements of B5G/6G applications. 3) Facilitating exceptional configurability is difficult, as it necessitates a flexible architecture that can serve multiple applications in the B5G/6G realm.