24.3 A 236-to-266GHz 4-Element Amplifier-Last Phased-Array Transmitter in 65nm CMOS.

Because the vast majority of the frequencies are unallocated and atmospheric absorption is low above 250GHz, 300GHz-band transceivers are appealing for the sixth-generation (6G) wireless communication technologies to support over 100Gb/s data rate. The main challenge of the 300GHz-band transmitter (TX) is achieving a large equivalent isotropic radiated power (EIRP) to compensate for the high free-space loss. One solution is to adopt a two-dimensional (2D) phased-array to boost the antenna gain and enable beam steering, which is much more practical than a high-gain antenna or lens. Another way is increasing the output power of each TX element. There are compound semiconductor processes with transistors exhibiting high unity-power-gain frequency (f max ) that can easily achieve this target; however, they tend to be incompatible with digital circuits and are expensive, which make them less practical. CMOS processes enable RF front-end circuits to integrate with baseband circuits at a much lower cost, but their low f max degrades power-amplifier (PA) performance. To address the f max limitation of CMOS, Fig. 24.3.1 shows some recent 300GHz-band TX architectures. The multiplier-last architecture can generate high TX output power, however, the constellation maps of higher-order modulation schemes are degraded and thus fail to support higher data rates [1]. To satisfy its mixer linearity requirement, the square mixer-last architecture needs to operate at power back-off (PBO), and it consumes a lot of area due to power-combining [2]. The sub-harmonic mixer-last architecture suffers from low output power and needs PBO in the TX [3]. While the outphasing topology can operate at around output power at 1dB compression point (OP 1dB ), the generation of the outphasing angles is problematic in digital baseband because their operation mechanism is intrinsically nonlinear [4]. Because of the absence of an RF PA, all the above works suffer from small EIRP, low power-added efficiency, and large chip area.