22.3 A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking.

Fast, low-power ADCs with $\sim 5 -6$ effective bits of resolution are a key element of 50+Gb/s links, which often use DSP-based equalization to compensate for high channel loss and high-order modulation schemes (e.g. PAM-4) to push link speed. Voltage-domain SAR ADCs are commonly time-interleaved (TI) to reach these speeds [1–2] but often require calibration-intensive techniques such as multi-comparator loop-unrolling [2] or pipelining to increase sub-ADC speed beyond $\sim 1$ GS/s, which is critical to reduce area and improve bandwidth by lowering capacitive input load. Time-domain ADCs can offer a fast ($\gt3{\mathrm{GS/s}}$), energy efficient [3] alternative well-suited to deeply scaled CMOS implementation. However, reliance on matched gate delays instead of capacitive weights either requires power-hungry phase interpolation or increases sensitivity to PVT variation and mismatch, which is detrimental to TI ADCs that need robust performance from all sub-ADCs. Hybrid voltage and time domain $( \mathrm{V}+\mathrm{T})$ ADCs [4–6] can bring the speed advantages of time-domain operation to voltage-domain ADCs. As in [4–5], in this work a voltage-to-time converter (VTC) acts as a high-speed buffer and a time-to-digital converter (TDC) operates in parallel with a time-to-voltage converter (TVC) to generate a coarse signal estimate to speed up a single-comparator SAR ADC. To improve upon prior art, this work uses the hybrid architecture to optimize the TI ADC floorplan and enhances reliability through (1) a VTC with common-mode input voltage tracking and (2) a merged flash TDC+TVC to guarantee TDC monotonicity with low added power. The 22nm CMOS prototype consumes 76mW at 40GS/s including input and reference buffers and achieves 32.3dB SNDR with a 20GHz input, for 57fJ/step ${\mathrm {FoM_{W}}}$.