18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS

An ADC/DAC-based coherent optical transceiver [1] is a promising technique to boost the throughput of metro/long-haul links beyond 600Gb/s/λ. It leverages the powerful digital signal processors (DSP) in scaled CMOS processes to enable high-spectral-efficiency modulation formats such as dual-polarization quadrature-amplitude modulation (DP-QAM). At the DSP interface, it uses four well-synchronized DACs and ADCs to generate and capture the four streams of analog signals that are carried by the same light in DP-QAM format (Fig. 18.1.1). In 600Gb/s links that use DP-QAM64 and feedforward error correction (FEC) coding, the baud rate can go up to 70GBaud/s. This requires an ADC/DAC bandwidth of 40GHz and a sampling rate of 105GS/s to satisfy the oversampling ratio needed for spectrum shaping and clock-data recovery. Meanwhile, the ADC/DAC have to achieve low noise and high linearity to achieve the SNDR needed for DP-QAM64 at low power consumption. In this paper, we present a 600Gb/s/λ DP-QAM64 coherent optical transceiver frontend that fully integrates a 4-way 78~105GS/s 8b ADC/DAC in a DSP chip in 16nm CMOS. It supports flexible rates of 100, 200, 300, 400, 500, 600Gb/s by DP-QPSK and DP-QAM8/16/32/64 with a variable baud rate for long-haul, metro, and ZR applications.